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Professional title:IC Design Manager/Supervisor/Director Design Engineer
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Wages:
Face to face
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Description:Shanghai
- Location of work: Shanghai - Shanghai - Huangpu District
- Department:Technology Department
- level：1
- Nature of work:Full time
- Age limitation for work:5-10 years
- Educational background:Master
- Gender:No limit
- Time of issue: 2025-06-12 17:30:00
Description:Shanghai
Description of position:
Responsibilities:
Lead the team or as an individual contributor to complete the company's leading voice processing SOC chip design, including but not limited to:
1. SoC subsystem division and interface definition
2. Module-level design, RTL coding and verification
3. Refine IP requirements according to product specifications, find and evaluate third-party IP.
4. Regularly carry out Design reviews and verification coverage analysis
5. Complete chip synthesis, equivalence analysis, timing analysis, coordinate back-end APR design, complete timing closure, FPGA verification and chip bring up Expected skills: Master's degree, more than 5 years (design manager needs more than 8 years) IC design project experience, or equivalent experience.
1. Familiar with and use Verilog HDL, and matlab/C/C++
2. Leading or participating in a number of chip front-end design projects from specifications to netlist.
3. Experience in SoC software and hardware co-design, verification and bring up
4. Have strong communication skills and organization and coordination skills, result-oriented
5. Having one or more of the following experience will be preferred: a) SOC architecture design, software and hardware division, multi-core heterogeneous SOC design b) Signal processing and hardware implementation of computer algorithms c) Familiar with common SOC components, such as on-chip bus architecture, level 2 cache/Flash Cache, DDR, USB, SDIO, CAN, QSPI Flash booting, etc. d) Practical experience in low-power design, such as multiple Vt, multiple Vdd, dynamic voltage scaling, etc.
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